The Joint Test Action Group (JTAG) Test Access Port and Boundary-Scan Architecture was originally defined to access and test integrated circuits (ICs) after installation on printed circuit boards (PCBs), and the methodology became Institute of Electrical and Electronic Engineers (IEEE)/American National Standards Institute (ANSI) Standard 1149.1. FIG. 1 schematically illustrates a conventional IEEE 1149 Boundary-Scan architecture. As shown in FIG. 1, the JTAG architecture (the IEEE 1149 standard) includes a test access port (TAP) 10 with four or five pins, and a chain of Boundary-Scan cells (BSCs) 12 surrounding internal logic 14 to be optionally tested. The four mandatory pins include two data pins: Test Data In (TDI) and Test Data Out (TDO), and two common pins: Test Clock (TCK) and Test Mode Select (TMS). A Test Reset (TRST) is an optional common pin. This architecture applies to the board and each IC which is part of the board.
FIG. 2 schematically illustrates an example of conventional BSC 12. The BSC 12 may be used at the input or output pins for the internal logic. During a normal operation the input signal is applied to the Data_In pin and passes trough a multiplexer 16 to the internal logic. When the cell is used as an output pin, the data from the internal logic are received at the Data_In and pass through the multiplexer 16 to the output of the chip. In the test mode, the data (test data) are coming through TDI, latched for internal testing or to be shifted to the next BSC when the clock is activated.
Although modern PCBs contain exotic IC packages which sometimes contain tens of millions of transistors, PCB designers still implement the JTAG (IEEE 1149) test port and scan chain using the methods unchanged in over a decade. Nowadays, however, the JTAG test interface, which complies with IEEE 1149 standard, is used for variety of applications. For example, the following applications are currently in use.
FIG. 3A schematically illustrates an example of a device chain (JTAG chain) 22 in the manufacturing test applications such as Boundary-Scan test or Built-in Self-test (BIST). The Boundary Scan test is a manufacturing test, in which test patterns are shifted into the device and driven out on the pins to external test points. An in-circuit test (ICT) fixture drives or reads these test patterns to test the PCB for open circuits, short-circuits, and other defects. The BIST is somewhat similar to the Boundary-Scan test except that the test patterns shifted in are used to trigger test sequences within the IC and to report the test results. As shown in FIG. 3A, a typical test configuration requirement is to wire all of the test devices 20 (20a, 20b, . . . ) into a single large chain 22 such that a TDO pin of a test device is connected to a TDI pin of the next test device. Each test device 20 may be a BSC, or other test device used in the BIST. The first test device 20a in the chain receives the test data from a TAP 24, and the TDO of last test device 20e in the chain is input to the TAP 24. The common signals TCK, TMS, and TRST are input to each of the test devices 20 from the TAP 24. The Data_In and Data_Out pins are coupled to external test points.
FIG. 3B schematically illustrates an example where a JTAG interface is used for downloading configuration data into programmable logic devices such as programmable logic devices (PLDs) or field programmable gate arrays (FPGAs) during laboratory bring-up or manufacturing. As shown in FIG. 3B, a programmable device 21 is configured via a connector 23 which interfaces to a computer or other programming fixture. The programmable device 21 may also be a group of programmable devices chained together for the purpose of this application.
FIG. 3C schematically illustrates an example where a JTAG interface is used to provide emulation tools with access to a central processing unit (CPU) or digital signal processor (DSP) core 25. Such a tool may be a development tool running on a laboratory computer connected to a PCB (or system under development) 27 via a cable. These tools are used during development, for example, to download code into a new CPU or DSP core, and to execute or debug the code.
FIG. 3D schematically illustrates an example where a JTAG interface is used to fix internal bugs contained in logic 31 which are already being used for a certain application. Typically, some internal logic is not accessible to the user in a normal operational mode. However, in many devices, vital registers and pieces of memory are accessible via the JTAG chain in a test mode. Thus, bugs or defects in early IC revisions, if any, can be corrected or bypassed by updating memory locations or setting bits in registers during initialization through the JTAG chain. A special bug-fixing logic 33 is typically required to be implemented for such bug-fixing.
However, a conventional JTAG chain topology (daisy chain) leads to certain common problems during design, debug, and manufacturing of the circuit due in part to the incompatible needs of various application as described below.
FIG. 4 schematically illustrates part of a conventional JTAG chain of mixed-voltage devices. As shown in FIG. 4, some devices in the chain may use different supply voltages and thus may have different requirements for voltage levels to be driven in on their TDI pin while the device is not powered up. For example, if a 5-V supply powers up a first device 30 while a second device 32 does not have power from a 3.3-V supply, an output signal of the first device 31 may damage the second device 32. Thus, different voltage parts may have to be electrically isolated from each other to avoid such damage. Conventionally, in order to avoid such damage, a buffer 34 is provided at the TDI and other inputs of the device 32, and the inputs are enabled only when a “power-good” signal is asserted. QUICC switch devices may also used to isolate devices with a different voltage requirement. However, these conventional solutions are costly and waste space since a buffer is required for each combination of devices having different operational voltage levels.
FIG. 5A schematically illustrates an example of a stuff option in a conventional JTAG chain including devices 36, 38, 40, and 42. Resistor stuff options are provided to a JTAG chain to implement a different topology to bypass one or more devices in the chain, typically in order to save cost. For example, if a customer design does not stuff the device 38, the output (TDO pin) 44 of the test device 36, which is originally routed to the TDI pin of the next device 38, has to be routed to the TDI pin 46 of the device 40. Such a re-route is conventionally implemented with a set of stuff option resistors 48 such that the TDO signal is re-routed to a TDI pin of a desired test device. FIG. 5B schematically illustrates such a re-routing where the stuff option resistor 48a is installed and the device 38 and corresponding option resistors are de-stuffed. The example in FIG. 5A is also capable of re-routing the TDO pin of the test device 36 to the TDI pin of the test device 42 when both of the test devices 38 and 40 are not stuffed. However, when a large number of stuff options need to be implemented, in addition to making the schematic complicated and hard to follow, there is a risk of introducing design errors and/or manufacturing errors into the system. Furthermore, in the case where a stuff option is not planned for in advance of the PCB fabrication, implementing it later almost always requires reworking or redesign of the PCB to correctly re-route the JTAG chain to support the stuff option.
As discussed above, the JTAG chain is also used to download configuration data into programmable devices such as PLDs or FPGAs. Since programmable devices are made by various vendors, a JTAG chain may include devices from different vendors, as shown in FIG. 5C. Since each vendor may use a different method or scheme to implement the download, a specific download or test scheme of one vendor may not be interoperable with another vendor's device which is in the way to the vendor's target device. This problem is typically not discovered until after PCB fabrication, and also requires to determine which vendor's scheme is incompatible with which vendor's devices. The only way around the problem is to isolate the incompatible vendor's devices on their own chain, as shown in FIG. 5D. This reconfiguration of the JTAG chain requires rework in the form of wires or redesign of the PCB for each particular application.
The isolation problem also occurs when the JTAG chain is used by various hardware emulation and debug tools as an interface with a processors such as CPU or DSP. Through the JTAG interface, code can be downloaded into the processor and output from the processor can be retrieved for debug. When initially bringing up a new processor, it may be required or desirable to have specific devices electrically isolated from the JTAG signals of other devices, for correct and efficient debug and fault isolation. Similarly, when one or more specific CPU or DSP devices need bug-fixing, as discussed above, the target device or devices should be electrically isolated from other devices. Without isolated accesses, the CPU or DSP devices may not operate correctly. In order to isolate one or more specific devises, the stuff option resistors are conventionally used to reconfigure the JTAG chain in the laboratory as explained above .